Design of TSV-sharing topologies for cost-effective 3D networks-on-chip

The Through-Silicon Via (TSV) technology has led to major breakthroughs in 3D stacking by providing higher speed and bandwidth, as well as lower power dissipation for the inter-layer communication. However, the current TSV fabrication suffers from a considerable area footprint and yield loss. Thus, it is necessary to restrict the number of TSVs in order to design cost-effective 3D on-chip networks. This critical issue can be addressed by clustering the network such that all of the routers within each cluster share a single TSV pillar for the vertical packet transmission. In some of the existing topologies, additional cluster routers are augmented into the mesh structure to handle the shared TSVs. However, they impose either performance degradation or power/area overhead to the system. Furthermore, the resulting architecture is no longer a mesh. In this paper, we redefine the clusters by replacing some routers in the mesh with the cluster routers, such that the mesh structure is preserved. The simulation results demonstrate a better equilibrium between performance and cost, using the proposed models

Adaptive routing methods for on-chip interconnection networks

For most of the history of computing, transistors have been expensive while wires have been cheap. Consequently, the focus has been on computational complexity, whereas the communication has been considered of secondary importance. With the continuous scaling in the semiconductor technology, the number of cores integrated into a single silicon chip is increased. Thus, we are entering a completely different era, where on-chip communication is being treated more and more as a “first-class citizen”. Networks-on-Chip (NoCs) have emerged as a promising communication approach to address the communication challenges associated with large-scale Multi-Processor Systems-on-Chip (MPSoCs). The overall performance of a NoC is strongly affected by the selection of the routing strategy as it impacts all network metrics, such as communication latency, throughput, power dissipation, silicon area, and reliability. This thesis revolves around the design of efficient routing approaches for NoC-based MPSoC architectures. In particular, the focus of this dissertation is the development of light-weight routing techniques for high-performance networks in three major contexts: 2D NoCs, 3D NoCs, and fault-tolerance. In this pursuit, we have proposed promising routing techniques in order to strike a balance between the conflicting goals of maximizing performance and reliability as well as minimizing power and area overhead

Hamiltonian path strategy for deadlock-free and adaptive routing in diametrical 2D mesh NoCs

The overall performance of Network-on-Chip (NoC) is strongly affected by the efficiency of the on-chip routing algorithm. Among the factors associated with the design of a high-performance routing method, adaptivity is an important one. Moreover, deadlock- and livelock-freedom are necessary for a functional routing method. Despite the advantages that the diametrical mesh can bring to NoCs compared with the classical mesh topology, the literature records little research efforts to design pertinent routing methods for such networks. Using the available routing algorithms, the network performance degrades drastically not only due to the deterministic paths, but also to the deadlocks created between the packets. In this paper, we take advantage of the Hamiltonian routing strategy to adaptively route the packets through deadlock-free paths in a diametrical 2D mesh network. The simulation results demonstrate the efficiency of the proposed approach in decreasing the likelihood of congestion and smoothly distributing the traffic across the network

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs

As silicon features approach the atomic scale, the Networks-on-Chip (NoCs) are becoming more susceptible to faults. Resiliency to device failures is, therefore, a key objective in the design of the Systems-on-Chip (SoCs). This paper seeks to address reliability by presenting a routing algorithm for 2D mesh NoCs. Using the proposed method which is designed based on the Abacus Turn Model (AbTM), the healthy paths can be dynamically configured according to the location of faults and congestion in the network. As a result, not only the functionality of the network is maintained in the vicinity of faults, but also a high performance communication can be provided. The presented technique is an adaptive, distributed, deadlock-free, and congestion-aware routing method which does not require routing tables or virtual channels. The experimental results demonstrate the reliability of NoC against multiple link failures with a small hardware overhead penalty

Adaptive and reconfigurable fault-tolerant routing method for 2D networks-on-chip

Networks-on-Chip (NoCs) are becoming more susceptible to faults due to the increasing density in the VLSI circuits. As a result, designing reliable and efficient routing methods is highly desirable. Most of the existing fault-tolerant routing techniques use nonminimal paths to reroute the packets around the faulty regions. Using these approaches, the network performance degrades drastically not only by taking unnecessary longer paths, but also by creating hotspots around the faults. Moreover, they are designed statically and cannot adapt to the dynamic traffic distribution in the network. In this paper, a reconfigurable and fault-tolerant routing method is proposed which is designed based on the Abacus Turn Model (AbTM). The presented deadlock-free routing technique is dynamically tuned based on the location of faults and congestion in the network. Thus, it is able to tolerate all single router failures without exploiting virtual channels. Moreover, it can grant full adaptiveness to the hotspot regions of the network. Using this scheme, the rerouting is minimized by forwarding the packets through the available shortest paths. This efficiency makes the proposed method a powerful asset for reliable routing in NoCs

Design and exploration of routing methods for NoC-based multicore systems

Routing methods have a crucial role in taking advantage of the potential benefits offered by Networks-on-Chip (NoCs). In this work, we address the design of routing techniques for NoC-based multicore systems through the application of turn model. Our work introduces different minimal and adaptive routing strategies which do not rely on Virtual Channels (VCs) for deadlock-freedom. The experimental results support our claim that the proposed algorithms can be used for efficient unicast/multicast routing in NoCs

3D MAX : a maximally adaptive routing method for VC-less 3D mesh-based Networks-on-Chip

The most valuable attribute of 3D Networks-on-Chip (NoCs) is the very small distance between the layers. Yet, this potential will go unrealized without the design of efficient routing methods. In this paper, we introduce 3D MAX, a maximally adaptive routing strategy for fully-connected 3D mesh networks. The proposed routing technique which is developed upon the EbDa theory exploits three key features to realize effective communication across the chip. First, from the turn model’s perspective, the minimum number of turns is prohibited such that the degree of routing adaptiveness is maximized. Second, 3D MAX is designed from an odd-even perspective in order to maintain a balanced traffic distribution. Third, the deadlock-freedom is guaranteed while eliminating the need for VCs or routing tables